1. Field of the Invention
The present invention relates to a gate driving device, and more particularly, to a gate driving device with current overdrive protection.
2. Description of the Related Art
A general gate driving device of an amorphous silicon thin film transistor liquid crystal display (TFT LCD) uses a high voltage to trigger the positioned horizontal amorphous silicon TFT so that the data of the source driving device can be transmitted to liquid crystal capacitors. Before the next horizontal line is going to be scanned, a negative high-voltage should be used to turn off the horizontal amorphous thin film transistors so as to maintain the data of the source driving device in the liquid crystal capacitors. The difference between the input and output voltages of the gate driving device can be tens of folds. Under an abnormal operation, the LCD or the gate driving device may be damaged.
Referring to FIG. 1, the gate driving device of the traditional amorphous silicon TFT LCD comprises a control-shift register circuit 10, a voltage level shifter 30, and a buffer block 40 with N high voltage buffer driving circuits. The control-shift register circuit 10 receives a activate pulse signal DIO, which can generate an activate pulse signal DOI for another gate driving device, a clock signal CLK, and an output enable signal OE. The voltage level shifter 30 receives and transforms the low-voltage logic signals into the positive/negative high-voltage (VGG and VEE) output signals. The high-voltage buffer driving circuits of the buffer block 40 are used to buffer the positive/negative high-voltage signals and to drive the output level device of the amorphous TFT LCD.
The gate driving device shown in FIG. 1 is under normal situation. Its input waveform is shown in FIG. 2A. When the gate driving device is activated by an activate pulse signal DIO, the first to the Nth high voltage horizontal lines are sequentially and individually enabled according to the clock signal CLK. The output enable signal OE is to prevent the output overlap between two neighboring horizontal lines. When signals are abnormally missed in the system, the timing controller will output abnormal signals and the gate driving device will be under abnormal situation. Referring to FIG. 2B, though the operations of the clock signal CLK and the output enable signal OE are normal, the activate pulse signal DIO is a pulse signal with a long period of time. As a result, the horizontal high-voltage output signals have N horizontal switches. IGG will generate a current spike between two output enable signals OE. Due to the high sudden current and the high average current, the circuit routes for high voltage on the LCD ITO (Indium tin oxide) are not sufficient and cannot stand the high current and will be damaged. In some situations, the gate driving device is latched and the LCD ITO is irreparably damaged.